An Efficient BIST Architecture for Embedded Dual-Port Memories
نویسندگان
چکیده
In this paper, a new algorithm and a new BIST structure for efficiently testing dual port memories that is used widely as embedded memory, is proposed. The proposed test algorithm is able to detect the dual port memories faults and has shorter test time and the test patterns in comparison to existing test algorithms. In addition, the presented BIST has efficient structure that requires lesser hardware overhead.
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